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Market analysis, feasibility studies and project start-up |
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Background research - future technology and technical analysis |
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Test equipment and hardware component evaluation |
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Technology White Papers |
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Technical presentations and English language documentation |
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DSL Performance & Interoperability Testing and Spectral Compatibility |
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Standardization and German Language Support |
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P E R S O N A L B A C K G R O U N D |
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I have a Masters degree in telecommunications systems, and most recently, I have been working on a mixture of hardware system
design and European standardization in the area of Digital Subscriber Line technology (HDSL, ADSL and SHDSL) at Keymile Ltd.
After joining what was then Ascom Hasler Ltd in 1986, I played a substantial role in the development of line terminal equipment
for 34 and 140 Mbit/s digital optical transmission system, and was quickly promoted to Group Leader in 1989.
From 1991 I led a team on study project for High Bit Rate Digital Subscriber Line (HDSL) technology, laying the foundation in
the company for the current xDSL products.Since 1992 I have been an active member of ETSI TM6 (initially TM3 WG12),
and from 1996 was secretary of the working group. As well as being directly involved with the first HDSL standard ETR-152,
(later TS 101 135) and the recent SDSL standard TS 101 524, I also carried out studies on subjects such as HDSL Performance
Testing and Jitter and Wander. I was particularly involved with xDSL measurement technicalities, and the influence of cable
characteristics and the effects of noise on the quality of xDSL systems, combining simulation analyses and practical measurements.
I also presented the results of my Spectral Measurement measurements and simulations to standards bodies, bringing the results of
the ensuing debate back into the DSL system design.
During market launchs I supported the product management with lectures and presentations for various customers.
I was involved in development projects as systems engineer in the analysis and preparation of use case models, for example
Defect detection and Fault Management models for SDH and ATM modules. I was also responsible for the evaluation of DSL chip
sets and POTS-DSL splitters, including custom analoge design of splitter circuits.
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